System and method for generating thermal network data and recording medium

ABSTRACT

A method for generating thermal network data for use in thermal analysis of a coupling structure of a large number of components. Depending on the density of nodes having a position defined by the structure, two-dimensional quadtree area division or three-dimensional octtree area division is performed. A node is provided in the center of the divided area and anode is determined using approximation to a node having a position defined by the structure. Alternatively, an area and a node are determined using Voronoi area division in case of area subdivision where a small area is assigned only to a defined node. Thermal network data is generated by inserting thermal resistances between respective nodes.

TECHNICAL FIELD

[0001] The present invention relates to a technology for generatingthermal network data, and more particularly to the technology forgenerating thermal network data for use in thermal analysis of acoupling structure of a plurality of components, such as a circuit boardhaving a large number of components mounted thereon.

BACKGROUND ART

[0002] Recently, as the downsizing of electronic apparatuses and theintegration of integrated circuits progress, thermal analysis during thedesign time becomes a factor indispensable to designing electronicapparatuses. Among the computing methods for thermal analysis is athermal network method which is widely known. As shown in FIG. 10, thethermal network method divides an analysis target into small areasaccording to its shape, boundary condition, and the like, and providesnodes for representing the temperatures of the small areas. This makesit possible to obtain solutions of high precision with computationalcomplexity of relatively small scale. In FIG. 10, focusing on a node Ni,the amount of heat occurring from the node Ni is given by:

(the amount of heat flowing out of the node Ni to a node N1)+(the amountof heat flowing out of the node Ni to a node N2)+ . . . +(the amount ofheat flowing out of the node Ni to a node Nj).

[0003] The thermal network method involves the operation of expressing atarget to be analyzed in the form of a thermal equivalent circuit asdescribed above. Initially, the internal of an electronic apparatus isdivided into several small areas. Representative points called nodes areprovided in these areas. A node is a point for representing thetemperature of a certain area, and typically falls on the center of thearea. Next, the nodes are coupled to each other with thermal resistancesso that the entire electronic apparatus is expressed in the form of athermal equivalent network. From the thermal network data thusgenerated, simultaneous linear equations are created which show theenergy balance between the individual areas. These equations can besolved to determine the temperatures and heat flow rates of the nodes.

[0004] In the area division of the conventional method for generatingthermal network data, uniform area division according to the shape ofthe analysis target is typically performed before nodes are establishedto generate thermal network data. As employed herein, “uniform areadivision” refers to dividing the area of a plurality of componentscoupled into small areas having a size necessary to show the couplingstate. For example, Japanese Patent Publication No. 2596847 discloses amethod of dividing an analysis target into rectangular small areas andadjusting mismatches between the small areas (see FIG. 11). Moreover,Japanese Patent Laid-Open Publication No. Hei 7-311166 describes amethod for area division and thermal resistance generation in which ananalysis target is initially divided into rectangular small areas, andthermal resistances are created from nodes to vertices of therectangular areas as necessary (see FIG. 12).

[0005] In recent years, scenes to generate thermal network data on acoupling structure of a large number of components, as typified by aprinted circuit board having a large number of components such as alarge-scale integrated circuit (LSI) mounted thereon, are on theincrease. In such cases, the conventional method for generating thermalnetwork data has the following problems.

[0006] A first problem occurs at the time of application of theconventional method for area division. In the conventional method forarea division, the uniform area division to a size necessary to show thecoupling state is performed on the entire area of a plurality ofcomponents coupled, thereby generating small areas. Consequently, when aplurality of components of large and small, various sizes are coupled inan area, the size of the small areas necessary to show the couplingstate becomes small. As a result, the number of small areas and thenumber of nodes increase to make the thermal network data larger inscale. Since the thermal network data, the input data of thermalanalysis, is of larger scale, it becomes difficult to apply the thermalanalysis during the design time. In other words, it becomes difficult tosecure practical calculation speed while ensuring the calculatingprecision.

[0007] For a second problem, the same problem as described above alsooccurs when the generation of thermal network data takes account of awiring pattern in addition to the coupling structure of a large numberof components. That is, the increase in the scale of the thermal networkdata makes it difficult to apply the thermal analysis during the designtime.

DISCLOSURE OF THE INVENTION

[0008] A first object of the present invention is to provide a system,method, and recording medium for generating thermal network data havingcomputational complexity of practical scale on a coupling structure of alarge number of components, typified by a printed circuit board having alarge number of components such as an LSI mounted thereon, therebyallowing thermal analysis.

[0009] A second object of the present invention is to provide a system,method, and recording medium for generating thermal network data havingcomputational complexity of practical scale, thereby allowing thermalanalysis even when the generation of the thermal network data also takesa wiring pattern into account. Here, the “practical scale” refers tosuch a scale of data that solutions can be obtained with a memory assmall as possible, at a high speed without a decrease in precision.

[0010] The following describes the means for achieving the first objectof the present invention. To give the rough meanings of terms used inthe following description, quadtree area division refers to square areadivision based on a certain rule. Octtree area division refers to cubicarea division based on a certain rule. Voronoi area division refers toarea division by means of assignment of areas to an arbitrary number ofpoints given in a plane or space. When a combination of a large numberof components is regarded as a plane (two-dimensional) structure, alarge number of node positions and areas are defined by constraint ofthe coupling structure of the components. Here, the plane structure issubjected to quadtree area division according to the density of suchposition-defined nodes, thereby generating two-dimensional small areasand nodes. Then, nodes generated by the quadtree area division, lyingnear the position-defined nodes are considered as lying approximately inthe same positions. The position-defined nodes are transferred to thenodes that are considered as lying in the same positions. Alternatively,the nodes that are considered as lying in the same positions may betransferred to the position-defined nodes. As above, in the areadivision on a two-dimensional structure, the algorithm of quadtree areadivision can be introduced to generate thermal network data of smallscale.

[0011] Even when a combination of a large number of components isregarded as a solid (three-dimensional) structure, a large number ofnode positions and areas are also defined by constraint of the couplingstructure of the components as is the case with a plane(two-dimensional) structure. Here, the solid structure is subjected toocttree area division according to the density of such position-definednodes, thereby generating three-dimensional small areas and nodes. Then,nodes generated by the octtree area division, lying near theposition-defined nodes are considered as lying approximately in the samepositions. The position-defined nodes are transferred to the nodes thatare considered as lying in the same positions. Alternatively, the nodesthat are considered as lying in the same positions may be transferred tothe position-defined nodes. As above, in the area division on a solidstructure, the algorithm of octtree area division can be introduced togenerate thermal network data of small scale as is the case with a planestructure.

[0012] In the area division by the foregoing means, the dividing process(subdivision) is iterated until the divided areas contain only a singlenode having a position defined by the constraint of the components to becoupled. In the process of such subdivision, small areas irrelevant toany defined node (containing no defined node) may also occur at the sametime. Then, in this process of subdivision, two-dimensional orthree-dimensional Voronoi area division is applied to perform areadivision if it is desired that small areas containing defined nodes begenerated exclusively (any small area containing no defined node not begenerated) to reduce the total number of nodes. Even when Voronoi areadivision is applied thus, the method using quadtree area division orocttree area division is used as the basis of the area division. Itbecomes therefore possible to generate thermal network data of smallscale as in the case with approximation.

[0013] The following describes the means for achieving the second objectof the present invention. Initially, a combination of a large number ofcomponents is subjected to quadtree area division (octtree area divisionif the target is regarded as three-dimensional). The divided areas aresubdivided further by quadtree area division under a condition setarbitrarily according to the density of a wiring pattern. Here, based onthe amounts of the wiring pattern passing through the subdivided smallareas, equivalent thermal resistances of the wiring in the areas aredetermined. Then, the parallel sums with thermal resistances occurringbetween the individual areas are worked out. This makes it possible togenerate thermal network data of small scale with the wiring patterntaken into account. Even when the wiring pattern is thus taken intoaccount, the method using quadtree area division or the like is used asthe basis of the area division. Besides, quadtree area division or thelike is further performed depending on the density of the wiringpattern. It becomes therefore possible to generate thermal network dataof small scale.

[0014] According to the method and system for generating thermal networkdata of the present invention, thermal analysis on a coupling structureof a large number of components, such as a printed circuit board havinga large number of electronic components mounted thereon, can beperformed with computational complexity of practical scale through theintroduction of the algorithm of quadtree area division or octtree areadivision. As a result, practical calculation speed is secured. The sameeffect can also be obtained when such an algorithm and Voronoi areadivision are used in combination. Furthermore, the influence of thewiring pattern can be reflected on the thermal network data without anincrease in analysis scale, thereby allowing more practical thermalanalysis.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a block diagram showing the configuration of a programfor use in the method of a first embodiment of the present invention;

[0016] FIGS. 2(a) and 2(b) are diagrams showing examples of thermalcharacteristics component data, FIG. 2(a) showing an example of LSI dataand FIG. 2(b) an example of PCB data;

[0017] FIGS. 3(a) and 3(b) are diagrams showing examples of componentlayout data, FIG. 3(a) showing wiring layout and FIG. 3(b) LSI layout;

[0018]FIG. 4(a) to 4(e) are flow diagrams showing the method of thefirst embodiment, FIG. 4(a) showing initial small areas, FIG. 4(b)subdivided areas, FIG. 4(c) a method of node approximation, FIG. 4(d)another method of node approximation, and FIG. 4(e) a thermal network;

[0019]FIG. 5 is a block diagram showing the configuration of a programfor use in the method of a second embodiment of the present invention;

[0020]FIG. 6 is a block diagram showing the configuration of a programfor use in the method of a third embodiment of the present invention;

[0021] FIGS. 7(a) to 7(d) are flow diagrams showing the method of thethird embodiment of the present invention, FIG. 7(a) showing initialsmall areas, FIG. 7(b) subdivided areas, FIG. 7(c) Voronoi areadivision, and FIG. 7(d) a thermal network;

[0022]FIG. 8 is a block diagram showing the configuration of a programfor use in the method of a fourth embodiment of the present invention;

[0023] FIGS. 9(a) to 9(c) are diagrams showing the processing of thefourth embodiment, FIG. 9(a) showing a wiring pattern, FIG. 9(b) smallareas taken account of the wiring pattern, and FIG. 9(c) thermalresistances of the wiring pattern;

[0024]FIG. 10 is a circuit diagram showing an example of a thermalnetwork used in conventional thermal analysis;

[0025]FIG. 11 is a plan view showing step by step the thermal analysisprocess described in a conventional art; and

[0026]FIG. 12 is a circuit diagram of a thermal network described inanother conventional art.

BEST MODE FOR CARRYING OUT THE INVENTION

[0027] Hereinafter, embodiments of the present invention are describedwith reference to the drawings. The following embodiments deals with thecases where a large-scale integrated circuit (LSI) is arranged on aprinted circuit board (PCB). Nevertheless, the method of the presentinvention is not limited to the combination of a PCB and an LSI, but iswidely applicable to the thermal analysis of targets having a couplingstructure of a large number of components.

[0028] For a first embodiment, description is initially given of thecase of applying quadtree area division, regarding the analysis targetof the thermal analysis as a plane structure (two-dimensionalstructure). FIG. 1 is a block diagram showing the configuration of aprogram for generating thermal network data for use in the method of thepresent embodiment. As shown in the diagram, the program includes: aninput data processing section 101 for inputting input data includingthermal characteristics component data, component layout data, andanalysis condition data; a plane structure area dividing section 102 forperforming quadtree area division; a plane structure thermal networkdata generating section 103 for outputting thermal network dataincluding thermal resistance data; and a thermal network analyzingsection 104 for outputting desired temperature and heat flow data.

[0029] The input data is composed of the thermal characteristicscomponent data and boundary condition data of components to be arrangedin an area, and the analysis condition data. These data must be preparedin advance for the sake of generating thermal network data. FIGS. 2(a)and 2(b) show examples of the thermal characteristics component data ofthe LSI and PCB which are the components in the LSI-PCB couplingstructure. As shown in the diagrams, the thermal characteristicscomponent data consists of a component type, dimension data showing theshape of the component, thermal resistance model data according to thecomponent type, material properties, and boundary condition data.

[0030] The component layout data consists of position data whichindicates the two-dimensional layout of the individual components. Theanalysis condition data is flag data for indicating whether to treat thetarget of the thermal analysis as a plane structure (two-dimensionalstructure) or a solid structure (three-dimensional structure), whetherto add Voronoi area division to the area division, whether to takeaccount of the wiring pattern in generating the thermal network data,and so on. Incidentally, in the present embodiment, the componentcoupling structure is treated as a plane structure. Voronoi areadivision is not added, and the wiring pattern is not taken into account.

[0031] The input processing section 101 reads and stores the input data.In the present embodiment, the input processing section 101 reads andstores the processing mode of “treating as a plane structure, adding noVoronoi area division, and not taking account of the wiring pattern,”and then passes the input data to the plane structure area dividingsection 102. Incidentally, the cases where Voronoi area division isadded and/or the wiring pattern is taken into account are detailedlater.

[0032] The plane structure area dividing section 102 determines whichcomponent to perform area division on according to the component type.In the coupling structure of the LSI and PCB in the present embodiment(FIGS. 3(a) and 3(b)), the thermal resistance data is previously knownof the LSI itself (FIG. 2(a)). Thus, area division shall not beperformed on the LSI but on the PCB alone. In the present embodiment,the plane structure area dividing section 102 consists of a quadtreearea dividing section alone. Then, the plane structure is subjected tothe quadtree area dividing section, so that the area is initiallydivided into an arbitrary number of square areas through quadtree areadivision. Nodes are provided at the centers of the areas (FIG. 4(a)).

[0033] When a combination of a PCB and a large number of LSIs isregarded as a two-dimensional (plane) structure, a large number of nodepositions and areas are defined by the constraint of the couplingstructure. Here, an example of the constraint is that a single componenthaving an unknown temperature distribution or a single structuralportion (shaped portion) of a certain component has at least one areaand a node having a position defined at the center. The term “node” ishereinafter used in two types of meanings. Nodes having a definedposition as above are referred to as “defined nodes.” The other nodes,provided in areas resulting from quadtree area division and the like,are referred to simply as “nodes” (FIG. 4(a)). Here, when a small areaof the PCB resulting from quadtree area division contains a plurality ofdefined nodes, subdivision is performed by using quadtree area divisionand nodes are provided (FIG. 4(b)). At the same time, the node lying inthe area before the subdivision is eliminated. The subdivision isiterated until a single small area contains a single defined node. Thesubdivision is ended when the number of defined nodes lying in a singlesmall area becomes one. Nodes that are determined to lie near thedefined nodes based on an index set arbitrarily are regarded as lying inthe same positions, and transferred to the defined nodes (FIG. 4(c)).Alternatively, the defined nodes are transferred to the nodes (FIG.4(d)). Such transfer of defined nodes means that the layout data ismodified by approximation for thermal analysis.

[0034] The small areas and node position data generated are passed tothe plane structure thermal network data generating section 103. Theplane structure thermal network data generating section 103 of thepresent embodiment consists of a thermal resistance data generatingsection alone. The thermal resistance data generating section generatesthermal resistance data on the substrate, the ground layer, and the likefrom their dimensions, sectional areas, and material properties. FIG.4(e) shows an example of thermal resistance data that is generated fromthe small areas and nodes generated by quadtree area division.

[0035] The thermal network data generated thus is input to the thermalnetwork analyzing section 104. Based on the thermal network data, thethermal network analyzing section 104 creates simultaneous linearequations showing the energy balance among the individual areas, andsolves these for thermal analysis. As a result, the temperature andthermal flow data of the nodes is obtained. Since the nodes are therepresentative points of the areas containing the nodes, the temperatureand heat flow data of the nodes shows the temperature and heat flow dataof the entire areas containing the nodes.

[0036] In the present embodiment, the introduction of the quadtree areadivision technique into the area division reduces the thermal networkdata and allows thermal analysis of practical scale. Repeating quadtreearea division until a single small area contains a single defined nodemeans that when there is no defined nodes to lie in a single small area,the area division need no longer be iterated on that small area.Finally, the area division is completed with as many nodes as the numberof the small areas. The amount of thermal network data is in proportionto the number of nodes. The ultimate number of areas can be reduced byenabling area division corresponding to the distribution of definednodes over the entire area of the target of the thermal analysis, orequivalently, by introducing the algorithm for such area division. Thereduction in the ultimate number of areas allows a reduction in theultimate number of nodes, and by extension a reduction of the thermalnetwork data. Consequently, it is possible to shrink the amount of thethermal network data, i.e., the computational complexity of the thermalanalysis without impairing the precision of the thermal analysiscomputation.

[0037] Next, for a method of a second embodiment of the presentinvention, description is given of the case where octtree area divisionis applied regarding the analysis target of the thermal analysis as asolid structure (three-dimensional structure). FIG. 5 is a block diagramshowing the configuration of a program for generating thermal networkdata according to the present embodiment. As shown in the diagram, itincludes: an input data processing section 501 for inputting thermalcharacteristics component data, component layout data, and analysiscondition data; a solid structure area dividing section 502 (octtreearea dividing section) 502; a solid structure thermal network datagenerating section 503 for generating thermal resistance data andoutputting thermal network data; and a thermal network analyzing section504 for outputting temperature and heat flow data.

[0038] The input data has the same configuration as in the firstembodiment. The component layout data, however, consists of positiondata that indicates the three-dimensional layout of the individualcomponents. Moreover, the analysis condition data is flag data forindicating whether to treat the target of the thermal analysis as aplane structure (two-dimensional structure) or a solid structure(three-dimensional structure), whether to add Voronoi area division tothe area division, whether to take account of the wiring pattern ingenerating a thermal network, and so on. The present embodiment dealswith the case of treating as a solid structure. Voronoi area division isnot added, and the wiring pattern is not taken into account.

[0039] The input processing section 501 reads and stores the input data.In the present embodiment, the input processing section 502 reads andstores the processing mode of “treating as a solid structure, adding noVoronoi area division, and not taking account of the wiring pattern,”and then passes the input data to the solid structure area dividingsection 502.

[0040] The solid structure area dividing section 502 determines whichcomponent to perform area division on according to the component type.In the coupling structure of the LSI and PCB in the present embodiment,the thermal resistance data is previously known of the LSI itself (FIG.2(a)). Thus, area division shall not be performed on the LSI but on thePCB alone. In the present embodiment, the solid structure area dividingsection 502 consists of an octtree area dividing section alone. Here,the solid structure is subjected to the octtree area dividing section,so that the area is initially divided into an arbitrary number of cubesby octtree area division. Nodes are provided at the centers of theareas.

[0041] When a combination of a PCB and a large number of LSIs isregarded as a solid structure (three-dimensional structure), a largenumber of node positions and areas are defined by the constraint of thecoupling structure. Again, as in the first embodiment, the two types ofnodes are referred to separately as “defined nodes” and “nodes.” When asmall area of the PCB resulting from the octtree area division containsa plurality of defined nodes, subdivision is performed using octtreearea division and nodes are provided. The repetition of subdivision andthe approximation-based transfer of nodes are the same as in the firstembodiment.

[0042] The three-dimensional small areas and node position datagenerated are passed to the solid structure thermal network datagenerating section 503. The solid structure thermal network datagenerating section 503 of the present embodiment consists of a thermalresistance data generating section alone. The thermal resistance datagenerating section generates thermal resistance data on the substrate,the ground layer, and the like from their dimensions, sectional areas,and material properties. The thermal network data generated thus isinput to the thermal network analyzing section 504. The thermal analysisand the generation of the temperature and heat flow data of the nodesare the same as in the first embodiment.

[0043] In the present embodiment, the introduction of the octtree areadivision technique into the area division as described above reduces thethermal network data and allows thermal analysis of practical scale.That is, since the octtree area division is a three-dimensionalapplication of the quadtree area division, the present embodimentprovides the same effects as in the first embodiment, allowing areduction in the amount of the thermal network data, i.e., thecomputational complexity of the thermal analysis without impairing theprecision of the thermal analysis computation.

[0044] Now, description is given of a third embodiment of the presentinvention. In the first and second embodiments, the quadtree areadivision or octtree area division and the approximation of nodepositions are used to determine node positions which are the basis ofthe thermal network data. As described above, in the area division bysuch means, subdivision is iterated until divided areas contain only asingle node having a position defined by the constraint of thecomponents to be coupled. In the process of such subdivision, smallareas containing no defined node may also occur at the same time. In thepresent embodiment, two-dimensional or three-dimensional Voronoi areadivision is applied in this process of subdivision if it is desired thatsmall areas containing no defined node not be generated, and the totalnumber of nodes be reduced.

[0045] The description is given of the case where quadtree area divisionis applied regarding the analysis target of the thermal analysis as aplane structure (two-dimensional structure), or octtree area division isapplied regarding it as a solid structure (three-dimensional structure).FIG. 6 is a block diagram showing the configuration of a program forgenerating thermal network data for use in the method of the presentembodiment. As shown in the diagram, the program includes: an input dataprocessing section 601 for inputting input data including thermalcharacteristics component data, component layout data, and analysiscondition data; a plane structure area dividing section 602 including aquadtree area dividing section 602 a and a two-dimensional Voronoiprocessing section 602 b; a solid structure area dividing section 604including an octtree area dividing section 604 a and a three-dimensionalVoronoi processing section 604 b; a plane structure thermal network datagenerating section 603 for generating thermal resistance data; a solidstructure thermal network data generating section 605 for generatingthermal resistance data and outputting thermal network data; and athermal network analyzing section 606 for outputting temperature andheat flow data.

[0046] The input data has the same configuration as in the foregoingembodiments. The analysis condition data is flag data for indicatingwhether to treat the target of the thermal analysis as a plane structure(two-dimensional structure) or a solid structure (three-dimensionalstructure), whether to add Voronoi area division to the area division,whether to take account of the wiring pattern in generating a thermalnetwork, and so on. In the present embodiment, the target is treated asa plane structure or a solid structure. Voronoi area division is added,and the wiring pattern is not taken into account.

[0047] The input processing section 601 reads and stores the input data.In the present embodiment, the input processing section 601 reads andstores the processing mode of “treating as a plane structure or a solidstructure, adding Voronoi area division, and not taking account of thewiring pattern,” and then passes the input data to the plane structurearea dividing section 602 or the solid structure area dividing section604.

[0048] The plane structure area dividing section 602 or the solidstructure area dividing section 604 determines which component toperform area division on according to the component type. The planestructure or the solid structure is subjected to the quadtree areadividing section 602 a or the octtree area dividing section 604 a,whereby the area is initially divided into an arbitrary number of squaresmall areas by quadtree area division or an arbitrary number of cubicsmall areas by octtree area division. Nodes are provided at the centersof the areas (FIG. 7(a)).

[0049] When a combination of a PCB and a large number of LSIs isregarded as a plane structure or a solid structure, a large number ofnode positions and areas are defined by the constraint of the couplingstructure. “Nodes” and “defined nodes” have the same meanings as in theforegoing embodiments. Here, if a PCB small area resulting from quadtreearea division or octtree area division contains a plurality of definednodes, the defined nodes are removed (FIG. 7(b)). The two-dimensionalVoronoi processing section 602 b or the three-dimensional Voronoiprocessing section 604 b performs Voronoi area division for theplurality of defined nodes, thereby generating small areas of anypolygonal shapes (FIG. 7(c)). Here, unlike in the first and secondembodiments, approximation-based node transfer is not performed.

[0050] The small areas and node position data generated are passed tothe plane structure thermal network data generating section 603 having athermal resistance data generating function or the solid structurethermal network data generating section 605 having a thermal resistancedata generating function. Thermal resistance data on the substrate, theground layer, and the like is generated therein from their dimensions,sectional areas, and material properties. FIG. 7(d) shows an example ofthermal resistance data that is generated from the small areas and nodesgenerated by using quadtree area division and Voronoi area division incombination. The thermal network data generated thus is input to thethermal network analyzing section 606. The thermal analysis and thegeneration of the temperature and heat flow data of the nodes are thesame as in the foregoing embodiments.

[0051] In the present embodiment, the technique of using the quadtreearea division or octtree area division and the Voronoi area division incombination can be introduced into the area division as described above.This reduces the thermal network data and allows thermal analysis ofpractical scale. In this case, the effect of reducing the number ofnodes through approximation as in the first and second embodiments isnot provided. Nevertheless, since the quadtree area division or octtreearea division according to the coupling structure of the components isused as the basis of the area division, it is possible to reduce theamount of the thermal network data than in conventional area division.

[0052] Now, for a fourth embodiment, description is given of the methodfor generating thermal network data with the thermal resistance of thewiring pattern also taken into account. In the present embodiment,quadtree area division is performed regarding the analysis target of thethermal analysis as a plane structure (two-dimensional structure), orocttree area division is performed regarding it as a solid structure(three-dimensional structure). Voronoi area division is also appliedwith one of these.

[0053]FIG. 8 shows the configuration of a program for generating thermalnetwork data for use in the method of the present embodiment. As shownin the diagram, it includes: an input data processing section 801 forinputting thermal characteristics component data, component layout data,analysis condition data, and wiring pattern data; a plane structure areadividing section 802 having a quadtree area dividing section 802 a and atwo-dimensional Voronoi processing section 802 b; a solid structure areadividing section 804 having an octtree area dividing section 804 a and athree-dimensional Voronoi processing section 804 b; a plane structurethermal network data generating section 803 having a thermal resistancedata generating section 803 a and a wiring pattern data generatingsection 803 b; a solid structure thermal network data generating section805 having a thermal resistance data generating section 805 a and awiring pattern data generating section 805 b; a thermal resistance datacoupling section 806 for outputting thermal network data; and a thermalnetwork analyzing section 807 for outputting temperature and heat flowdata.

[0054] The input data of the present embodiment is that of theembodiments described so far to which the wiring pattern data is added.The analysis condition data is flag data for indicating whether to treatthe target of the thermal analysis as a plane structure (two-dimensionalstructure) or a solid structure (three-dimensional structure), whetherto add Voronoi area division to the area division, whether to takeaccount of the wiring pattern in generating a thermal network, and soon. The present embodiment deals with the case of treating as a planestructure or a solid structure. Voronoi area division may or may not beadded, and the wiring pattern is taken into account.

[0055] The input processing section 801 reads and stores the input data.In the present embodiment, the input processing section 801 reads andstores the processing mode of “treating as a plane structure or as asolid structure, adding or not adding Voronoi area division, and takingaccount of the wiring pattern,” and then passes the input data to theplane structure area dividing section 802 or the solid structure areadividing section 804.

[0056] The plane structure area dividing section 802 or the solidstructure area dividing section 804 further subdivides divided smallareas by quadtree area division or octtree area division under a uniformdensity condition which is set arbitrarily according to the density ofthe wiring pattern (FIG. 9(a)) as in the foregoing embodiments. Thesubdivided areas are provided with nodes while the nodes having been inthe areas before the subdivision are eliminated (FIG. 9(b)). Therepetition of the subdivision, the approximation, and the application ofVoronoi area division are the same as in the embodiments described sofar.

[0057] The small areas and node position data generated are passed tothe plane structure thermal network data generating section 803. Thethermal resistance data generating section 803 a or 805 a initiallygenerates thermal resistance data on the substrate, the ground layer,and the like with consideration given to the thermal resistance modeldata, material properties, and boundary condition data out of the inputdata without taking account of the thermal resistance of the wiringpattern. Next, the wiring pattern thermal resistance data generatingsection 803 b or 805 b determines equivalent thermal resistances in thesmall areas based on the amounts of the wiring pattern passing throughthe subdivided small areas (FIG. 9(c)). Here, thermal resistancesbetween nodes taking account of the wiring pattern are defined as theparallel sums of equivalent thermal resistances of the wiring patternand the previously-generated thermal resistances between the smallareas. According to this definition, the thermal resistance datacoupling section 806 generate the thermal network data of the entirestructure of the analysis target. The thermal network data generatedthus is input to the thermal network analyzing section 807. The thermalanalysis and the generation of the temperature and heat flow data of thenodes are the same as in the foregoing embodiments.

[0058] In the present embodiment, the application of quadtree areadivision and the octtree area division to the area division makes itpossible to generate thermal network data of practical computationscale. Moreover, even when the wiring pattern is taken into account,subdivision is performed through the application of the quadtree areadivision according to the density of the wiring pattern. It is thereforepossible to reduce the amount of the thermal network data.

Industrial Applicability

[0059] The method and system for generating a thermal network of thepresent invention are used to generate a thermal network for use inthermal analysis of various apparatuses having a coupling structure of aplurality of components, such as a printed circuit board having LSI andother components mounted thereon.

1. A thermal network data generating method for generating thermalnetwork data for use in thermal analysis targeted at a couplingstructure of a plurality of components, said method comprising the stepof: dividing an area of said coupling structure by applying eitherquadtree area division regarding the analysis target as atwo-dimensional structure or octtree area division regarding theanalysis target as a three-dimensional structure.
 2. A thermal networkdata generating system for generating thermal network data for use inthermal analysis targeted at a coupling structure of a plurality ofcomponents, said system comprising: an area dividing section fordividing an area of said coupling structure by applying either quadtreearea division regarding the analysis target as a two-dimensionalstructure or octtree area division regarding the analysis target as athree-dimensional structure.
 3. A thermal network data generating systemfor generating thermal network data for use in thermal analysis targetedat a coupling structure of a plurality of components, said systemcomprising: an input data processing section for selecting either aprocess regarding the analysis target as a two-dimensional structure ora process regarding the analysis target as a three-dimensional structurebased on an analysis condition, and determining a component on which anarea division is to be performed based on a component type; an areadividing section for performing one of dividing processes includingquadtree area division regarding the analysis target as atwo-dimensional structure and octtree area division regarding theanalysis target as a three-dimensional structure, iterating saiddividing process until each area divided by said dividing processcontains only a single node having a position defined by constraint ofcomponents to be coupled, providing a node at a predetermined positionof each area divided by said dividing process, and considering, amongnodes having positions defined by the constraint of said components tobe coupled, one of the nodes lying in a vicinity of nodes positioned atthe predetermined positions of the areas divided by said dividingprocess as lying approximately in the same positions as those of thenodes positioned at the predetermined positions of the areas based on anindex set arbitrarily; and a thermal network data generating section forgenerating thermal network data for connecting together determined nodesvia thermal resistances having thermal resistance values according tothe sizes and properties of said components to be coupled.
 4. A thermalnetwork data generating system for generating thermal network data foruse in thermal analysis targeted at a coupling structure of a pluralityof components, said system comprising: an input data processing sectionfor selecting either a process regarding the analysis target as atwo-dimensional structure or a process regarding the analysis target asa three-dimensional structure based on an analysis condition, anddetermining a component on which area division is to be performed basedon a component type; an area dividing section for performing one ofdividing processes including quadtree area division regarding theanalysis target as a two-dimensional structure and octtree area divisionregarding the analysis target as a three-dimensional structure,providing a nodes at the center of each area divided by said dividingprocess, eliminating, if a single small area divided by said dividingprocess contains a plurality of nodes each having a position defined byconstraint of components to be coupled, the node positioned at thecenter of the small area having the plurality of nodes each having theposition defined by the constraint of said components to be coupled, andapplying Voronoi area division to the single small area containing theplurality of nodes each having the position defined by the constraint ofsaid components to be coupled, so as to generate further small areashaving nodes each having the position defined by the constraint of saidcomponents to be coupled as representative points thereof; and a thermalnetwork data generating section for generating thermal network data forconnecting together determined nodes via thermal resistances havingthermal resistance values according to the sizes and properties of saidcomponents to be coupled.
 5. The thermal network data generating systemaccording to claim 3 or 4, wherein: said area dividing section, inaddition to performing said dividing process, further subdivides theareas divided by said dividing process based on the density of a wiringpattern laid in the analysis target subjected to said dividing process,under a uniform density condition set arbitrarily; and said thermalnetwork data generating section, in addition to performing thegeneration of the thermal network data for connecting together thedetermined nodes via the thermal resistances having the thermalresistance values according to the sizes and properties of saidcomponents to be coupled, determines equivalent thermal resistances insaid small areas based on the amounts of said wiring pattern passingthrough said subdivided areas and defines thermal resistances asparallel sums of said equivalent thermal resistances in said small areasbased on to the amounts of said wiring pattern and saidpreviously-generated thermal resistances between the nodes.
 6. Thethermal network data generating system according to any one of claims 3to 5, wherein said coupling structure of the plurality of components isa coupling structure of a large-scale integrated circuit and a printedcircuit board.
 7. A thermal network data generating method forgenerating thermal network data for use in thermal analysis targeted ata coupling structure of a plurality of components, said methodcomprising the steps of: selecting one from between quadtree areadivision regarding the analysis target as a two-dimensional structureand octtree area division regarding the analysis target as athree-dimensional structure based on an analysis condition; determininga component on which area division is to be performed based on acomponent type; performing a dividing process selected from between saidquadtree area division and said octtree area division; iterating saiddividing process until areas divided by said dividing process containonly a single node having a position defined by constraint of componentsto be coupled; providing a node at the centers of each area divided bysaid dividing process; considering, among nodes having positions definedby the constraint of said components to be coupled, one of the nodeslying in a vicinity of a node positioned at the center of the areadivided by said dividing process as lying approximately in the sameposition as that of the node positioned at the center of the area basedon an index set arbitrarily; and generating thermal network dataconnecting together determined nodes via thermal resistances havingthermal resistance values according to the sizes and properties of saidcomponents to be coupled.
 8. A thermal network data generating methodfor generating thermal network data for use in thermal analysis targetedat a coupling structure of a plurality of components, said methodcomprising the steps of: selecting one from between quadtree areadivision regarding the analysis target as a two-dimensional structureand octtree area division regarding the analysis target as athree-dimensional structure according to an analysis condition;determining a component on which area division is to be performed basedon a component type; performing a dividing process selected from betweensaid quadtree area division and said octtree area division; positioninga node at the center of each area divided by said dividing process;eliminating, if a single small area divided by said dividing processcontains a plurality of nodes each having a position defined byconstraint of components to be coupled, the node provided at the centerof the single small area containing the plurality of nodes having theposition defined by the constraint of said components to be coupled, andapplying Voronoi area division to the single small area containing theplurality of nodes having the position defined by the constraint of saidcomponents to be coupled, so as to generate further small areas havingthe nodes having the positions defied by the constraint of saidcomponents to be coupled as representative points thereof; andgenerating thermal network data for connecting together determined nodesvia thermal resistances having thermal resistance values according tothe sizes and properties of said components to be coupled.
 9. Thethermal network data generating system according to claim 7 or 8,further comprising the steps of: subdividing the areas divided by saiddividing process based on the density of a wiring pattern laid in theanalysis target divided by said dividing process, under a uniformdensity condition set arbitrarily; and determining equivalent thermalresistances in said small areas based on the amounts of said wiringpattern passing through said subdivided areas, and defining thermalresistances as parallel sums of the equivalent thermal resistances insaid small areas based on the amounts of said wiring pattern and thepreviously-generated thermal resistances between the nodes.
 10. Arecording medium containing a program for allowing a computer to executethe thermal network data generating method according to claim 7 or 8.